- RS庫存編號:
- 171-3349
- 製造零件編號:
- 74VHC573FT
- 製造商:
- Toshiba
當前暫無庫存,可於2024/9/2發貨,3 工作日送達。
已增加
單價 个(每带 2500 )
HK$1.558
單位 | Per unit | Per Reel* |
2500 - 2500 | HK$1.558 | HK$3,895.00 |
5000 - 7500 | HK$1.511 | HK$3,777.50 |
10000 + | HK$1.466 | HK$3,665.00 |
* 參考價格 |
- RS庫存編號:
- 171-3349
- 製造零件編號:
- 74VHC573FT
- 製造商:
- Toshiba
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
The 74VHC573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages
Wide operating temperature range: Topr = -40 to 125
High speed: fMAX = 180 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC/LV etc.) 573 type.
High speed: fMAX = 180 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC/LV etc.) 573 type.
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.
規格
Attribute | Value |
---|---|
Logic Family | 74VHC |
Latch Mode | Transparent |
Latching Element | D Type |
Number of Elements per Chip | 19 |
Number of Bits | 8bit |
Number of Channels per Chip | 8 |
Polarity | Inverting |
Mounting Type | Surface Mount |
Package Type | TSSOP |
Pin Count | 20 |
Dimensions | 6.5 x 4.4 x 1mm |
Height | 1mm |
Length | 6.5mm |
Minimum Operating Supply Voltage | 2 V |
Width | 4.4mm |
Automotive Standard | AEC-Q100 |
Minimum Operating Temperature | -40 °C |
Maximum Operating Supply Voltage | 5.5 V |
Maximum Operating Temperature | +125 °C |