onsemi MC100EPT25DGOS, Logic Level Translator Translator ECL to LVTTL, 8-Pin SOIC-NB

The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 μF capacitor.

1.1ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V, VEE = -5.5 V to -3.0 V, GND = 0 V
24mA TTL outputs
Q Output will default LOW with inputs open or at GND
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available

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