ON Semiconductor, MC100EPT26DTG


The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. The VBB output allows the EPT26 to be used in a single-ended input mode. In this mode the VBB output is tied to the D0bar input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the VBB pin should be bypassed to ground via a 0.01 uF capacitor.

1.4ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
Safety Clamp on Inputs
24mA TTL outputs
Q Outputs will default LOW with inputs open or at VEE VBB Output

LVDS Communication

Low Voltage Differential Signaling, or LVDS, is an electrical signaling system that can run at very high speeds over cheap, twisted-pair copper cables.

Applications: Firewire, SATA, SCSI

Attribute Value
Logic Function Translator
Maximum High Level Output Current -3mA
Maximum Low Level Output Current 24mA
Output Type TTL
Maximum Propagation Delay Time @ Maximum CL 4.1 ns @ 20 pF
Mounting Type Surface Mount
Package Type TSSOP
Pin Count 8
Dimensions 3.1 x 3.1 x 1.95mm
Height 1.95mm
Length 3.1mm
Maximum Operating Supply Voltage 3.6 V
Maximum Operating Temperature +85 °C
Width 3.1mm
Propagation Delay Test Condition 20pF
Minimum Operating Supply Voltage 3.6 V
Minimum Operating Temperature -40 °C
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