Microchip DSPIC33CH128MP502-I/SS, Microprocessor dsPIC33CH 16bit DSP, MCU 180 MHz, 200 MHz 28-Pin SSOP
- RS庫存編號:
- 175-7198
- 製造零件編號:
- DSPIC33CH128MP502-I/SS
- 製造商:
- Microchip
可享批量折扣
小計(1 包,共 2 件)*
HK$82.60
訂單超過 HK$250.00 免費送貨
最後的 RS 庫存
- 最終 128 個,準備發貨
單位 | 每單位 | 每包* |
|---|---|---|
| 2 - 10 | HK$41.30 | HK$82.60 |
| 12 - 22 | HK$40.50 | HK$81.00 |
| 24 + | HK$39.65 | HK$79.30 |
* 參考價格
- RS庫存編號:
- 175-7198
- 製造零件編號:
- DSPIC33CH128MP502-I/SS
- 製造商:
- Microchip
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Microchip | |
| Family Name | dsPIC33CH | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | DSP, MCU | |
| Maximum Frequency | 180 MHz, 200 MHz | |
| Fabrication Technology | CMOS | |
| Mounting Type | Surface Mount | |
| Package Type | SSOP | |
| Pin Count | 28 | |
| Typical Operating Supply Voltage | 3 → 3.6 V | |
| Dimensions | 10.5 x 5.6 x 1.85mm | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | +85 °C | |
| 選取全部 | ||
|---|---|---|
品牌 Microchip | ||
Family Name dsPIC33CH | ||
Data Bus Width 16bit | ||
Instruction Set Architecture DSP, MCU | ||
Maximum Frequency 180 MHz, 200 MHz | ||
Fabrication Technology CMOS | ||
Mounting Type Surface Mount | ||
Package Type SSOP | ||
Pin Count 28 | ||
Typical Operating Supply Voltage 3 → 3.6 V | ||
Dimensions 10.5 x 5.6 x 1.85mm | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature +85 °C | ||
- COO (Country of Origin):
- TH
System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller (DSC) with two dsPIC DSC cores in a single chip. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application.
Operating Conditions
3V to 3.6V, -40°C to +125°C
Core: Dual 16-Bit dsPIC33CH CPUs
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Programmable PLLs and Oscillator Clock Sources
Fast Wake-up and Start-up
Backup Internal Oscillator
Low-Power Management Modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
Debugger Development Support
3V to 3.6V, -40°C to +125°C
Core: Dual 16-Bit dsPIC33CH CPUs
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Programmable PLLs and Oscillator Clock Sources
Fast Wake-up and Start-up
Backup Internal Oscillator
Low-Power Management Modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
Debugger Development Support
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
相关链接
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